SYLLABUS

Course objective
This course aims to provide a strong foundation in the principles of digital systems and
logic design. It introduces number systems, Boolean algebra, and techniques for designing
combinational and sequential circuits. The course also explores memory devices and
programmable logic components essential for modern digital systems.
Digital fundamentals
Number Systems – Decimal, Binary, Octal, Hexadecimal, 1’s and 2’s complements, Codes
– Binary, BCD, Excess 3, Gray, Alphanumeric codes, Boolean theorems, Logic gates, Universal
gates, Sum of products and product of sums, Min terms and Max terms, Karnaugh map
Minimization and QuineMcCluskey method of minimization.
Combinational logic design
Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder –
Carry look ahead Adder, BCD Adder, Binary Multiplier, Multiplexer, Demultiplexer, Magnitude
Comparator, Decoder, Encoder, Priority Encoder
Synchronous sequential circuits
Flip flops – SR, JK, T, D, Master/Slave. FF operation and excitation tables, Triggering
of FF, Analysis and design of clocked sequential circuits – Moore/Mealy models, state
minimization, state assignment, circuit implement – Design of Counters – Ripple Counters:
Binary, BCD, Modulo n, Up/Down counters-Counter for Random Sequence – Shift registers:
Universal ShiftRegister – Synchronous counter Ringercounter-Johnson counter.
Asynchronous sequential circuits
Analysis and design of Asynchronous sequential circuits-reduction of Flow Tables – Stable
and Unstable states, state reduction, output specifications, cycles and races, race free assignments,
Hazards: Essential Hazards, Pulse mode sequential circuits, Design of Hazard free circuits.
Memory and programmable logic circuits
ROM – PROM – EPROM – EEPROM – EAPROM, RAM – Programmable Logic Devices
– Programmable Logic Array (PLA) – Programmable Array Logic (PAL) – Field Programmable
Gate Arrays (FPGA) – Implementation of combinational circuits using PLA, PAL, CPLD’s.
TTL and CMOS Logic families
Hardware description language
Introduction to verilog: Structure of verilog module, operators, data types, styles of
description – Data flow description, Implement logic gates, half adder and full adder using
Verilog data flow description, Behavioral description: Structure, variable assignment statement,
sequential statements, loop statements, Verilog behavioral description of Multiplexers (2:1, 4:1,
8:1) and De-multiplexers – encoders (8 to 3), Decoders (2 to 4) latches – flipflops.